System and method of background offset cancellation for flash adcs

ABSTRACT

A background offset cancellation technique based on interleaved auto-zero (IAZ) architecture for flash ADCs, moves the reference tap values up and down to accommodate auto-zeroing of differential comparators rather than switching the differential comparator reference point between two distinct reference taps. The technique eliminates a large number of complementary switches necessary to provide the reference tap values leading to substantial savings in area and power, and provides for improved settling characteristics of the reference ladder.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] This invention relates generally to high-speed flashanalog-to-digital converters (ADCs), and more particularly to a methodof background offset cancellation for flash ADCs based on interleavedauto-zero (IAZ) architecture.

[0003] 2. Description of the Prior Art

[0004] Comparators are used in flash ADCs to compare the input voltagewith the reference voltage generated by the reference ladder and make adecision based on the relative value of the input voltage with respectto the reference voltage. Differential comparators with frequentauto-zeroing are used for high-speed flash ADCs having 6 or more bits ofresolution. The advantages of fully differential schemes include reducedcharge injection error, high common-mode signal noise rejection andincreased immunity to the power supply and substrate noise. Fullydifferential comparators are indispensable to achieve high resolutionfor flash ADCs operating in a mixed-signal environment. The minimumresolution of a comparator is limited by its offset voltage and the lowfrequency 1/f noise. Techniques such as auto-zeroing serve to cancel thecomparator offset, reduce its low frequency 1/f noise and sample thereference levels for comparison with the input. During the comparisonphase, the stored reference value is subtracted from the input and theresult is amplified by the comparator to output a decision. Auto-zeroingis essential for high-resolution flash ADCs. Typically, a comparator isauto-zeroed every clock cycle by assigning a portion of the clock periodfor auto-zeroing and the remaining portion for conversion. Frequentauto-zeroing is desirable for obtaining high resolution, but it causesvarious transient noises, kickback noise to the reference resistorladder, and power supply noise during the transition from auto-zeroingto comparison and from comparison to auto-zeroing. Further, since thereis an auto-zeroing period between two comparison periods, continuousconversion is not possible. Various other problems present in thisconventional interleaved auto-zeroing implementation include: 1) Sincehalf of the conversion cycle time is spent on auto-zeroing, only half ofthe clock period is available for conversion, requiring the comparatorcircuit to be designed at twice the operating speed; 2) As the frequencyof operation increases, the amount of time available for auto-zeroingshortens; 3) Kickback noise occurs on the reference ladder when thecomparator is auto-zeroed; and 4) The resistance of the reference ladderis determined by the RC time constant during the auto-zeroing phase fora given sampling capacitor size; and since this time constant is afraction of the operating clock period, the resistance of the referenceladder depends on the conversion rate.

[0005] The foregoing and other like problems restrict high-speed ADCoperation and makes it difficult to operate the ADC in a mixed-signalenvironment. In order to reduce various transient noises and to achievecontinuous conversion, it is desirable to reduce the auto-zeroing ratewithout requiring an extra auto-zeroing period for the whole ADC and todesign a high-speed comparator that compares several times with oneauto-zeroing.

SUMMARY OF THE INVENTION

[0006] To meet the above and other objectives, the present inventionprovides an offset cancellation technique that performs offsetcancellation in the background (i.e. without interruptinganalog-to-digital conversion) by using one extra comparator slice and bymaking the auto-zeroing period independent of the operating clockperiod. The time available for the conversion process is thus extendedwhile the state transition period between auto-zeroing and comparison isreduced. At any instance of time, one comparator is auto-zeroed whilethe remaining comparators perform A/D conversion.

[0007] In one aspect of the invention, a background offset cancellationcircuit that employs differential comparators and that is suitable foruse with a high-speed flash ADC having 6 or more bits of resolution isimplemented to reduce the number of complementary switches necessary toprovide reference tap values leading to substantial saving in die area.

[0008] In another aspect of the invention, a background offsetcancellation circuit that employs differential comparators and that issuitable for use with a high-speed flash ADC having 6 or more bits ofresolution is implemented to reduce the series switch resistance and theparasitic junction capacitances in the reference voltage path, improvingthe settling characteristics of the reference ladder.

[0009] In yet another aspect of the invention, a background offsetcancellation circuit that employs differential comparators and that issuitable for use with a high-speed flash ADC having 6 or more bits ofresolution is implemented to minimize the size and the power consumptionof the clock driver(s) necessary to operate the complementary switchesassociated with setting reference tap values needed for auto-zeroing.

[0010] In still another aspect of the invention, a background offsetcancellation circuit that employs differential comparators and that issuitable for use with a high-speed flash ADC having 6 or more bits ofresolution is implemented to simplify the layout of the comparatorslice.

[0011] In still another aspect of the invention, a background offsetcancellation circuit that employs differential comparators and that issuitable for use with a high-speed flash ADC having 6 or more bits ofresolution is implemented to cancel the offsets of the operationalamplifier and remove the finite gain error.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other aspects and features of the present invention, and many ofthe attendant advantages of the present invention, will be readilyappreciated as the same become better understood by reference to thefollowing detailed description when considered in connection with theaccompanying drawings in which like reference numerals designate likeparts throughout the figures thereof and wherein:

[0013]FIG. 1 is a block diagram illustrating a conventional flash ADCusing an interleaved auto-zeroing (IAZ) technique that is known in theprior art;

[0014]FIG. 2 is a waveform timing diagram illustrating timingrelationships for various signals associated with the conventional flashADC using IAZ shown in FIG. 1;

[0015]FIG. 3 is a schematic diagram illustrating a typical referencevoltage tap switching implementation using a differential scheme for theconventional flash ADC using IAZ shown in FIG. 1;

[0016]FIG. 4 is a schematic diagram illustrating a conceptualimplementation of a background offset cancellation circuit architectureaccording to one embodiment of the present invention;

[0017]FIG. 5 is a schematic diagram illustrating one actualimplementation of a background offset cancellation circuit architectureaccording to one embodiment of the present invention;

[0018]FIG. 6 is a schematic diagram illustrating one actualimplementation of a background offset cancellation circuit architecturewhich cancels the offset of the operational amplifiers according to oneembodiment of the present invention; and

[0019]FIG. 7 is a detailed waveform timing diagram illustrating timingrelationships for various signals associated with the background offsetcancellation circuit architecture shown in FIG. 6.

[0020] While the above-identified drawing figures set forth particularembodiments, other embodiments of the present invention are alsocontemplated, as noted in the discussion. In all cases, this disclosurepresents illustrated embodiments of the present invention by way ofrepresentation and not limitation. Numerous other modifications andembodiments can be devised by those skilled in the art which fall withinthe scope and spirit of the principles of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0021]FIG. 1 is a block diagram illustrating a conventional flash ADC100 using an interleaved auto-zeroing (IAZ) technique for a 6-bitconverter that is known in the prior art. For convenience, asingle-ended version is shown, but in practice, a fully-differentialversion is generally implemented. Reference voltages, generated by areference resistor ladder 102, are depicted as V_(RL), V_(R1), V_(R2), .. . V_(R63), V_(RH). Comparators 104 are depicted as C₁, C₂, C₃, . . .up to C₆₄.

[0022]FIG. 2 is a waveform timing diagram 200 illustrating timingrelationships for various signals associated with the conventional flashADC 100 using IAZ shown in FIG. 1. During time t₀, all the comparators(C₁-C₆₄) 104 are auto-zeroed with reference voltages V_(RL)-V_(R63)respectively, before the conversion starts. During the next period t₁,all comparators 104 are set to the comparison state and the conversionis achieved by comparators C₂-C₆₄. During the next period t₂, comparatorC₁ that was auto-zeroed with V_(RL) during t₀, is now auto-zeroed withV_(R1) while the conversion is achieved by C₂-C₆₄. During the nextperiod t₃, comparator C₂ that that was previously auto-zeroed withV_(R1) during t₀, is now auto-zeroed with V_(R2) and the conversion isachieved by C₁ and C₃-C₆₄. A sixty-four to sixty-three multiplexer 106after the comparators 104 selects the valid comparator 104 outputs to abubble correction circuit 108 and a thermometer code encoder 110. AfterC₆₄ is auto-zeroed with V_(RH) during t₆₅, switches (S_(1H)-S_(64H)) 112turn off and switches (S_(1L)-S_(64L)) 114 turn on (t₆₆-t₆₇) and C₆₄ isagain auto-zeroed with V_(R63) during t₆₈. Then C₆₃ is auto-zeroed withV_(R62) during t₆₉ and the sequence goes on until C₁ is auto-zeroed withV_(RL) during t₁₃₁. Finally, switches (S_(1L)-S_(64L)) 114 turn off andswitches (S_(1H)-S_(64H)) 112 turn on (t₁₃₂-t₁₃₃) and again C₁ isauto-zeroed with V_(R1). The foregoing sequence of events repeatscontinuously during A/D conversion. The required rate of auto-zeroing isdetermined by the rate of charge leakage from the sampling capacitor inthe comparator 104 for a particular technology.

[0023] The IAZ architecture shown in FIG. 1 functions with only twocomparators changing state once every n comparisons (assuming that theauto-zeroing period is n times the comparison+reset period): one fromauto-zeroing to comparison and the other from comparison toauto-zeroing. In a conventional ADC, all comparators change states twicefor every comparison. Significant features of the IAZ architecturedepicted in FIG. 1 include: 1) High-speed conversion is possible sincethe whole clock period is available for conversion; 2) Kickback noiseand the power supply noise can be reduced since all comparators 104 donot perform auto-zeroing at the same time; 3) Auto-zeroing period isindependent of the conversion time and its duration can be setindependently according to the ladder settling time dictated by thereference ladder 102 resistance, the comparator load resistance, theseries switch (e.g., 306, 308 in FIG. 3) resistance and the samplingcapacitance value; 4) Power consumption in the reference ladder 102 canbe reduced by setting the high reference ladder resistance 120. This ispossible since the auto-zeroing period can be set independently of theconversion period; and 5) Because of the reduced state transitionbetween the auto-zeroing and comparison, the overall power consumptionis reduced.

[0024] During time period t₀-t₆₅, all the comparators (C₁-C₆₄) 104 areconnected to the reference taps V_(R1)-V_(RH) respectively, as statedherein before. It was shown that after t₆₅, switches (S_(1H)-S_(64H))112 turn off and switches (S_(1L)-S_(64L)) 114 subsequently turn onduring time period t₆₆-t₆₇, such that all the comparators (C₁-C₆₄) 104are then connected to the reference taps V_(RL)-V_(R63) respectively.After t₁₃₁, all the comparators (C₁-C₆₄) 104 are again connected to thereference taps V_(R1)-V_(RH) respectively, and the sequence goes on,also stated above. Since the reference voltage value is always stored inthe capacitance during auto-zeroing and is subtracted from Vin duringconversion, moving of the reference voltage taps does not affectconversion and hence does not cause any systematic offset.

[0025]FIG. 3 is a schematic diagram illustrating a typical referencevoltage tap switching architecture 300 for the conventional flash ADC100 using IAZ shown in FIG. 1. When the comparator (C_(i)) 104 isauto-zeroed during the clock phase φ₁, sampling capacitors C_(s+) andC_(s−) sample the reference voltages V_(R+) and V_(R−) respectively, atone end and the offset of the comparator at the other end. Switches 310,312 connected around the opamp 104 and controlled by the clock signalφ_(1a) are opened first to reduce the input dependent charge injectionas known in the prior art. The clock signal φ_(1a) is similar to φ₁except that its falling edge precedes the falling edge of φ₁ in time.During the clock phase φ₂, the input signal is sampled relative to thestored reference value and a comparison is made. Reference tap switchingis achieved by connecting the reference point V_(R+) of the comparator(C_(i)) 104 (i=1-64) to either of the two reference taps (V_(R+), andV_(R+) _(i−1) ) 314, 316 and by connecting V_(R−) of the comparator(C_(i)) 104 (i=1-64) to either of the two reference taps (V_(R−), andV_(R−) _(i−1) ) 302, 304 respectively by using four additional switches306, 308, 318, 320 as shown in FIG. 3. When φUD is high, V_(R+) isconnected to V_(R+), and V_(R−) is connected to V_(R−) _(i−1) throughswitches 318, 306 respectively. Similarly, when {overscore (φ)}UD ishigh, V_(R+) is connected to V_(R+) _(i−1) and V_(R−) is connected toV_(R−) _(i−1) through switches 320, 308 respectively. Since theseswitches 306, 308, 318, 320 to the reference taps (V_(R+) _(i) ,V_(R+)_(i−1) ,V_(R−) _(i) and V_(R−) _(i−1) ) 314, 316, 302, 304 are normallycomplementary type switches for wider analog input range, eight extratransistors (four ‘n’ and four ‘p’) are necessary per comparator 104slice. Hence, for an n-bit Flash converter, a total of 8×2^(n) extratransistors are required. These additional transistors are problematicbecause: 1) A large number of switches are required to switch betweenthe reference ladder taps for comparison, which occupies a significantamount of die area; 2) Since all the switches are driven by a commonclock-driver, the clock driver has to be huge, again increasing theamount of required die area. Further, driving such a large loadpresented by these switches consumes significant amounts of power; 3)Since two complementary switches are connected to each tap in theladder, the capacitance at each tap is twice compared to that presentedusing the conventional non-interleaved auto-zeroing scheme and increasesthe settling time of the reference ladder; and 4) The series switchresistance of the switches 306, 308, 318, 320 connecting the referencetap to the sampling capacitor adds to the Thevenin equivalent resistanceat a given tap, and hence degrades the settling time of the referenceladder

[0026]FIG. 4 is a schematic diagram illustrating a conceptualdifferential implementation of a background offset cancellation circuitarchitecture 400 according to one embodiment of the present invention.The problems discussed above with reference to the voltage tap switchingarchitecture 300 shown in FIG. 3 are solved with the circuitarchitecture 400 by connecting the comparators 104 to the reference taps402-416 in a conventional manner (i.e. V_(R+) and V_(R−) are directlyconnected to the reference taps without using the series switches 306,308, 318, 320 as shown in FIG. 3) and then moving the reference tapvalues up and down by ½ LSB (for differential configuration). Since thebottom switch 420 is directly in the current path when it is closed, andsince the switches have a finite “on” resistance, this implementationintroduces a constant systematic offset and also prevents implementationof accurate reference tap 402-416 values. One embodiment of a circuitarchitecture that overcome these problems while taking advantage of theconceptual technique described with reference to FIG. 4 is shown in FIG.5.

[0027]FIG. 5 is a schematic diagram illustrating one actualimplementation of a background offset cancellation circuit 500 accordingto one embodiment of the present invention. The background offsetcancellation circuit 500 can be seen to include a reference currentsource 502 in the V_(RL) leg 510 as well as a reference current source504 in the V_(RH) leg 530. The reference current sources 502, 504 shouldbe identical to eliminate any mismatches between them. The V_(RL) leg510 provides reference voltages V_(R1−), V_(R2−), V_(R3−), . . . ,V_(R63−) and V_(RL). The V_(RH) leg 530 provides reference voltagesV_(R1+), V_(R2+), V_(R3+), . . . , V_(R63+) and V_(RH). The V_(RL) leg510 has a switching transistor 512 that is activated by an op-amp 514that has a feedback loop implemented with a pair of switches 516, 518and one resistor 520 that forms one resistor ladder element of theV_(RL) leg 510. The V_(RH) leg 530 has a switching transistor 532 thatis activated by an op-amp 534 that has a feedback loop implemented witha pair of switches 536, 538 and one resistor 540 that forms one resistorladder element of the V_(RH) leg 530. The comparators 104 are connectedto resistor taps 522-528 and 542-548 in a fashion such as shown in FIG.4. The reference voltage at each resistor tap 522-528, 542-548 is thenswitched up and down by ½ LSB as the auto-zeroing and conversionprocesses advance in a manner such as discussed herein before withrespect to FIGS. 1-3. Sources of mismatch affecting the DNL, apart fromresistance mismatches include mismatch in the current sources 502, 504.It can be noted that the offsets of the op-amps 514, 534 in FIG. 5results only in a finite gain error in the overall ADC transfercharacteristics and can be corrected by an offset cancellation scheme asshown in FIG. 6 discussed herein below. The present inventor found thatthe op-amps 514, 534 notably can be high-gain/low bandwidth types sincethe time period for two complete auto-zero cycles (e.g. t₆₆-t₆₇ as shownin FIG. 2) is available between successive auto-zeroing; and hence thereis sufficient time for the reference ladder values to settle to theircorrect values. Moreover, the auto-zeroing sequence starting from t₆₈ asshown in FIG. 2 can be delayed by a suitable amount of time for theresistor ladder to adequately settle before performing the auto-zeroingof comparator C₆₄ with the V_(R63) reference tap value. The internalimplementation of the differential comparator and generation of signal{overscore (φ)}UDR is also shown in FIG. 5.

[0028] The circuit architecture shown in FIG. 5 advantageouslyeliminates the need for a large number of switches (and hencetransistors), leading to substantial savings in die area and powerconsumption. A further advantage is obtained since the layout of thecomparator slice is also simplified. The clock driver for the switches516, 518, 536, 538 can also be very small since it has to drive now fouradditional complementary switches as compared to (8×2^(n)) additionalcomplementary switches required for the scheme shown in FIG. 3,discussed herein before. This reduces the power necessary to operate theclock driver resulting in further savings in IC power consumption.Another advantage of the circuit architecture shown in FIG. 5 is thedecreased value of stray capacitance at each reference tap. Thereference taps (n₁₊, n₂₊, . . . , n₆₄₊, and n¹⁻, n²⁻, . . . , n⁶⁴⁻) aredirectly connected to the sampling capacitor C_(S) of each comparatorC_(i) (i=1-64) as shown in FIG. 5. Hence, the capacitance at eachreference tap (n₁₊, n₂₊, . . . , n₆₄₊, and n¹⁻, n²⁻, . . . , n⁶⁴⁻) ishalf as compared to the earlier scheme due to the elimination of twoparallel switches present at each reference tap in FIG. 1. This improvesthe settling time as compared to the conventional scheme. Anotheradvantage is that the Thevenin equivalent resistance at a givenreference tap is now determined only by the reference ladder resistance‘R’ and the series switch resistance of the respective switch connectingthe reference tap to the capacitance C_(S). The present scheme theneliminates one series switch in the path from the reference tap toC_(S), resulting in a reduced Thevenin equivalent resistance at thereference tap. This improves the settling characteristics of theresistance ladder during auto-zeroing.

[0029]FIG. 6 is a schematic diagram illustrating a circuit architecture600 to cancel the offsets of the operational amplifiers 514, 534discussed herein before, according to one embodiment of the presentinvention. Finite offsets of the opamps 514, 534 scale the voltage stepsdefined by the resistor ladders 510, 530 proportionately, resulting in afinite gain error in the overall ADC transfer characteristics. In someapplications, this can be problematic. The background offsetcancellation circuit 600 shown in FIG. 6 is an implementation to correctthis finite gain error resulting due to opamp offsets. The backgroundoffset cancellation circuit 600 can be seen to include offset sensingcapacitors (CB) 602, 604 connecting the positive input of theoperational amplifier 514 to node 606 and the negative input of theoperational amplifier 534 to node 608. As can also be seen, switches610, 612 and 618 have been added to switches 516 and 518, and switches614, 616 and 620 have been added to switches 536 and 538 to furtherimplement the background offset cancellation circuit 600. Switches 610,516, 612, 518 and 618 are controlled by clock signals φU, φ_(ru), φD,φ_(rdr) and φ_(reset) respectively, while switches 616, 536, 614, 538and 620 are controlled by clock signals φU, φ_(ru), φD, φ_(rdr) andφ_(reset) respectively. The auto-zeroing is now controlled by twonon-overlapping clock phases, φU and φD, instead of the single clocksignal φUD shown in FIG. 2. Clock signal φ_(ru) is high after clockphase φD goes low and before clock phase φU goes high; and clock signalφ_(rd) is high after clock phase φU goes low and before clock phase φDgoes high. The offset cancellation of the opamps 514, 534 is performedduring φ_(reset). During φ_(reset), switches 618 and 620 are closed,connecting the capacitor C_(B) 602 between the positive input of theoperational amplifier 514 and V_(RL) rererence voltage at the negativeinput of the opamp 514; while another capacitor C_(B) 604 is connectedbetween the negative input of the operational amplifier 534 and V_(RH)reference voltage at the positive input of the opamp 534. Further,either of the switches (518 and 538) controlled by φ_(rd) or (516 and536) controlled by φ_(ru) is high closing the feedback loop around theoperational amplifiers 514, 534 in the switching circuit. The capacitorsC_(B) 602 and C_(B) 604 sample offset voltages of the operationalamplifiers 514 and 534 respectively until φ_(rd) or φ_(ru) is high. Thefalling edge of φ_(reset) is delayed with respect to the falling edge ofφ_(rd) or φ_(ru) so that the charge injection of switch 518 and switch538 when φ_(rd) goes low or of switch 516 and switch 536 when φ_(ru)goes low, only matters. The charge injection of these switches (516,518, 536, 538) can be minimized by either using complementary typetransistors exactly balancing their charge injection or by using anadditional half-sized dummy transistor via techniques familiar to thoseskilled in the art. When φU or φD goes high, the reference tap valuessettle to their correct value after the offset of the operationalamplifiers 514, 534 are cancelled because of the capacitor C_(B) (602,604) included in the feedback loop. One embodiment of a simple clockgeneration circuit 650 suitable for use with the background offsetcancellation circuit 600 generates clock signal φ_(rdr), whiledifferential comparator circuit 690 illustrates one internalimplementation of a differential comparator suitable for use with thebackground offset cancellation circuit 600. When the reset signal RES ishigh, φ_(rdr) is high and the reference taps n₆₄₊, n₆₃₊, . . . , n₁₊assume the reference values V_(R63+), V_(R62+), . . . , V_(cm) while thereference taps n⁶⁴⁻, n⁶³⁻, . . . , n¹⁻ assume the reference valuesV_(R63−), V_(R62−), . . . , V_(cm) respectively.

[0030]FIG. 7 is a waveform timing diagram 700 illustrating timingrelationships for various signals associated with the background offsetcancellation architecture 600 using IAZ shown in FIG. 1. Initially, whenthe reset signal RES is high, the reference tap values at n₆₄₊, n₆₃₊, .. . , n₁₊ are V_(R63+), V_(R62+), . . . , V_(cm), and at n⁶⁴⁻, n⁶³⁻, . .. , n¹⁻ are V_(R63−), V_(R62−), . . . , V_(cm) respectively, as statedherein before. During time to, all the comparators (C₁-C₆₄) 104 areauto-zeroed with reference voltages V_(R0)-V_(R63) respectively, beforethe conversion starts. During time t₁, φ_(reset) and φ_(ru) are high andthe reference tap values at n₆₄₊, n₆₃₊, . . . , n₁₊ are V_(RH),V_(R63+), . . . , V_(R1+) and at n⁶⁴⁻, n⁶³⁻, . . . , n¹⁻ are V_(RL),V_(R63−), . . . , V_(R1−) respectively. The offset cancellation of theopamps (514, 534) is also carried out during t₁. During t₂, φU goes highand the reference tap values settle at their correct values after theoffset has been cancelled. Further, during t₁ and t₂, all comparators104 are set to the comparison state and the conversion is achieved bycomparators C₂-C₆₄. During the next period t₃, comparator C₁ that wasauto-zeroed with V_(R0) during to is now auto-zeroed with V_(R1) whilethe conversion is achieved by C₂-C₆₄. During the next period t₄,comparator C₂ that was previously auto-zeroed with V_(R1) during to isnow auto-zeroed with V_(R2) and the conversion is achieved by C₁ andC₃-C₆₄. A sixty-four to sixty-three multiplexer 106 after thecomparators 104 selects the valid comparator 104 outputs to a bubblecorrection circuit 108 and a thermometer code encoder 110 as shown inFIG. 1. After C₆₄ is auto-zeroed with V_(RHL) during t₆₆, φU goes lowand φ_(reset) and φ_(rd) go high by the end of t₆₇. During t₆₈, again,the opamp offset cancellation is carried out and the reference tapvalues at n₆₄₊, n₆₃₊, . . . , n₁₊ are V_(R63+), V_(R62+), . . . ,V_(cm), and at n⁶⁴⁻, n⁶³⁻, . . . , n¹⁻ are V_(R63−), V_(R62−), . . . ,V_(cm) respectively. Also, during t₆₈-t₆₉, the switches (S_(1H)-S_(64H))112 turn off and switches (S_(1L)-S_(64L)) 114 turn on and the referencetaps settle to their correct values after the opamp offset has beencancelled. During t₆₉, φD goes high and C₆₄ is again auto-zeroed withV_(R63) during t₇₀. Then C₆₃ is auto-zeroed with V_(R62) during t₇₁ andthe sequence continues on until C₁ is auto-zeroed with V_(R0) duringt₁₃₃. The switches (S₁L-S_(64L)) 114 turn off at the end of t₁₃₄ andswitches (S_(1H)-S_(64H)) 112 turn on during t₁₃₅ when φ_(reset) andφ_(ru) again go high and the opamp offset cancellation is being carriedout. Finally, during t₁₃₇, C₁ is auto-zeroed with V_(R1) and thesequence continues.

[0031] In summary explanation, a differential comparator auto-zeroingscheme suitable for use with a high-speed flash ADC, reduces theauto-zeroing rate without requiring an extra auto-zeroing period for thewhole ADC, and further provides a high-speed comparator that comparesseveral times with only one auto-zeroing. The scheme performs offsetcancellation in the background by using one extra comparator slice andby making the auto-zeroing period independent of the operating clockperiod to extend the available conversion time. The scheme employs aunique circuit architecture that eliminates a large number of switches(transistors) such that the clock driver for the switches can be madevery small, resulting in substantially reduced power consumption andimproved settling characteristics of the reference resistor ladderduring auto-zeroing. The scheme described herein also corrects thefinite gain error in the overall ADC transfer characteristic due to theoffset of the operational amplifiers used in switching the referencetaps.

[0032] In view of the above, it can be seen the present inventionpresents a significant advancement in the art of background offsetcancellation circuit technology associated with flash ADCs. Further,this invention has been described in considerable detail in order toprovide those skilled in the data communication art with the informationneeded to apply the novel principles and to construct and use suchspecialized components as are required. In view of the foregoingdescriptions, it should further be apparent that the present inventionrepresents a significant departure from the prior art in constructionand operation. However, while particular embodiments of the presentinvention have been described herein in detail, it is to be understoodthat various alterations, modifications and substitutions can be madetherein without departing in any way from the spirit and scope of thepresent invention, as defined in the claims which follow. For example,although various embodiments have been presented herein with referenceto particular transistor types, the present inventive structures andcharacteristics are not necessarily limited to particular transistortypes or sets of characteristics as used herein. It shall be understoodthe embodiments described herein above can easily be implemented usingmany diverse transistor types so long as the combinations achieve abackground offset cancellation technique for flash ADCs according to theinventive principles set forth herein above.

What is claimed is:
 1. A background offset cancellation circuitcomprising: a first resistor ladder having a plurality of referencetaps, the first resistor ladder connected at its first end to a firstreference current source and further connected at its opposite end to afirst switching circuit; and a second resistor ladder having a pluralityof reference taps, the second resistor ladder connected at its first endto a second reference current source and further connected at itsopposite end to a second switching circuit; wherein the first switchingcircuit is operational in response to a clock driver signal to changesignal values at each first resistor ladder reference tap, and whereinthe second switching circuit is operational in response to the clockdriver signal to change signal values at each second resistor ladderreference tap.
 2. The background offset cancellation circuit accordingto claim 1 wherein the first switching circuit comprises: a firstswitching transistor having a control terminal driven by a firstoperational amplifier, and further having a current input terminal and acurrent output terminal; a feedback resistor connecting the currentinput terminal to the opposite end of the first resistor ladder; a firstcomplementary switch connecting a positive input of the firstoperational amplifier to the current input terminal; and a secondcomplementary switch connecting the positive input of the firstoperational amplifier to the opposite end of the first resistor ladder,wherein the first and second complementary switches operate incomplement with one another and in response to the clock drive signal,and further wherein the first resistor ladder reference tap signalvalues move up and down in response to operation of the first and secondcomplementary switches.
 3. The background offset cancellation circuitaccording to claim 2 wherein the second switching circuit comprises: asecond switching transistor having a control terminal driven by a secondoperational amplifier, and further having a current input terminal and acurrent output terminal; a feedback resistor connecting the secondswitching transistor current output terminal to the opposite end of thesecond resistor ladder; a third complementary switch connecting anegative input of the second operational amplifier to the secondswitching transistor current output terminal; and a fourth complementaryswitch connecting the negative input of the second operational amplifierto the opposite end of the second resistor ladder, wherein the third andfourth complementary switches operate in complement with one another inresponse to the clock drive signal, and further wherein the secondresistor ladder reference tap signal values move up and down in responseto operation of the third and fourth complementary switches.
 4. Thebackground offset cancellation circuit according to claim 1 wherein thefirst and second resistor ladders each comprise the same number ofreference taps.
 5. The background offset cancellation circuit accordingto claim 4 wherein the first and second resistor ladders comprise solelyof resistors having a single common value.
 6. The background offsetcancellation circuit according to claim 5 wherein each switching circuitfeedback resistor has a value equal to the single common value.
 7. Thebackground offset cancellation circuit according to claim 6 wherein thefirst reference current source is further connected to a supply voltage.8. The background offset cancellation circuit according to claim 7wherein the second reference current source is further connected to acircuit ground.
 9. The background offset cancellation circuit accordingto claim 1 further comprising a plurality of differential comparators,wherein each differential comparator is operational to receive arespective first resistor ladder reference tap signal during a firsttime period and a corresponding second resistor ladder reference tapsignal during the first time period, and a respective first resistorladder reference tap signal moved by ½ LSB during a second time periodand a corresponding second resistor ladder reference tap signal moved by½ LSB during the second time period, wherein the first and second timeperiods are determined by the clock driver signal.
 10. A backgroundoffset cancellation circuit comprising: a first resistor ladderconnected at one end to a first reference current source and having aplurality of reference taps; a second resistor ladder connected at oneend to a second reference current source and having a plurality ofreference taps; means for changing signal values up and down at eachfirst resistor ladder reference tap; and means for changing signalvalues up and down at each second resistor ladder reference tap.
 11. Thebackground offset cancellation circuit according to claim 10 wherein themeans for changing signal values up and down at each first resistorladder reference tap comprises a first switching circuit connectedbetween an opposite end of the first resistor ladder and a circuitground.
 12. The background offset cancellation circuit according toclaim 11 wherein the means for changing signal values up and down ateach second resistor ladder reference tap comprises a second switchingcircuit connected between an opposite end of the second resistor ladderand a voltage supply.
 13. A method of canceling offset and 1/f noise inbackground in a flash ADC, comprising the steps of: providing a flashADC having a plurality of differential comparators and a matched pair ofresistor ladders, each resistor ladder connected to a signal levelshifting circuit, each resistor ladder having a plurality of referencetaps such that each reference tap on one resistor ladder corresponds toa reference tap on the other resistor ladder to create a plurality ofpairs of corresponding reference taps; passing a reference currentthrough each resistor ladder such that a reference tap signal isgenerated at each reference tap to provide a plurality of pairs ofcorresponding reference tap signals and such that each pair ofcorresponding reference tap signals can provide a differential referencetap value, wherein each reference tap signal is associated with areference tap value; and shifting each reference tap value up and down apredetermined amount in response to a clock driver signal.
 14. Themethod according to claim 13 further comprising the step of connectingeach pair of corresponding reference tap signals to a respectivedifferential comparator such that each differential comparator can beauto-zeroed in response to reference tap signals having values that moveup and down by a predetermined amount in response to the clock driversignal to perform auto-zeroing.